Module BTE5482: System on Chip Design

Course Description

See official description

Course Schedule and Material

This is the course syllabus of the course System on Chip Design

A 6 minute overview presentation for the top down track is given in this slides.

Accompanying course material for the Bachelor course System-on-Chip Design (SoC) can be found on this page. The course will be presented in two parallel tracks, top down and bottom up track. With the mixed two down and bottom und approach a good balance between the abstract higher level and easier to follow lower level subjects can be reached. A serie of practical hands-on CAD exercises accompany the course theory. Be aware that there are some formatting problems in the top down handout text versions. The slides of the first four chapters, Introduction, Methodology, Modeling and Hardware Sythesis are a copy of Gajski's transparencies with some minor changes and some additional animations for didactical purposes. The slides accompany his book Embedded System Design (which is mandatory for this course) contain some summary text notes.


Course Organization 2015

The course organisation is summarized by these slides.

System-on-Chip (top down track)

System-on-Chip (top down track, optional)

VLSI (bottom up track)

VLSI Testing (bottom up track, optional)

Short Questions

The weekly short questions are assembled in this pdf.

VLSI (optional stuff requested by students)

Analog Microelectronics (optional analog track)

Laboratories and Exercises

The links and files for the SoC laboratories are given below.

  • Full Custom Design with Cadence and a general purpose 45 nm process technology[Tutorial]<
  • (old version) Full Custom Design with Cadence and AMS HIT-Kit [Tutorial]
  • FSMD + ModelSim exercise files [ZIP]
  • Introduction to the Digital Workflow with Synopsys and Cadence [Tutorial]

If there is sufficient time left, the following exercises on ESE are recommended. The Embedded System Environment (ESE) is a new tool for System Level Design. It was developed by the Center for Embedded Computer Systems at the University of California, Irvine.

The hands-on CAD laboratories will be done at the HuCE-microLab on a Linux based environment. For a quick overview over the most important commands, have a look at the following PDF documents.

  • Linux Quick reference with examples [PDF]
  • Linux Quick reference [PDF]

Laboratories and Exercises (optional)

For the platform based design exercises the Xilinx FPGA EDK tool chain will be used in combination with the HuCE-microLab GECKO system design platform.


During the class, the assessment is done by a test at the end of the course.

  • Sample assesment test during class [PDF]

The final exams are orally, students have the possibilty to propose to study an additional subject from literature they want to present at the final exams by some slides (maximum 10 min). Students using this possibility must have approved the subject by the lecturer in advance. A small report must be handed in at least 1 weak before the final exams.